The present invention relates to an arithmetic processing module associated with a microprocessor central processing unit, with a sequencer and with a working memory of the read-write type, for performing an operation corresponding to the general formula: EQU B=a.X+T
in which B, X and T are high value integers and a is an operand having a format restricted to m bits, this operation being produced during a sequence of successive computing steps consisting in combining the operand a with operands x.sub.i and t.sub.i having a format restricted to n bits, which are respectively extracted from the integers X and T, at the rank of significance i taken in increasing order, and in storing the partial result b.sub.i, of the same significance rank and also forming an extract having a format restricted to n bits of the complete result B, the processing module comprising inputs for the operands a, x.sub.i and t.sub.i and an output for the result b.sub.i, a multiplier for performing the product a.x.sub.i, followed by a first adder and a second adder, the second adder supplying a partial operation result which can be divided into a most significant portion and a least significant portion which is capable of being directed on output as a result b.sub.i, the operand t.sub.i being applied to one of the inputs of one of the adders and the most significant portion of a preceding computing step being applied to one of the inputs of the other adder by means of a recycling storage unit.
The invention is more particularly but not exclusively aimed at small sized systems where the function of processing a digital information is executed by a single integrated circuit, of the microcontroller type. In such a circuit, a very strict compromise must be sought between the speed of execution of the processing and the implementation of a minimum number of components, in order to satisfy both the requirements of manufacturing cost and those of the duration of execution of the processing. A particularly significant example in this respect is represented by the miniaturized device of the "smart card" (or "chip card") type capable of multiple applications, for example: exchange of bank data, access control, signature authentication, etc.
When the data processing comprises a large number of similar arithmetic operations, it is advantageous to couple to a central processing unit (CPU), for which rather general management functions are reserved, a specialized processing module capable of performing a certain type of arithmetic and/or logic operation at high speed and of doing this in a relatively independent manner with respect to the central processing unit, at least while a sequence of consecutively concatenated operations is being performed.
A processing module of this type and complying with the definition given in the introductory paragraph is known from the patent application FR-A-2 613 861.
As this is a device principally intended to be incorporated in a microcontroller for a smart card it is necessary to try to economize as much as possible on the memory requirements to be integrated on the microcontroller chip and also to make best use of the clock speed which, according to current technologies, is rather limited. Finally, the sought objective is that the processing duration should be acceptable by the user, for example the waiting time for a processing result should remain, if possible, less than or in the order of one second.
An analysis of the known processing module shows that its operation must be frequently interrupted particularly for loading new data to be processed under the control of the central processing unit. These interruptions necessarily cause a very significant slowing down of the overall data processing operation.